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ltc2607/ltc2617/ltc2627 26071727fa block diagram features description 16-/14-/12-bit dual rail-to-rail dacs with i 2 c interface the ltc ? 2607/ltc2617/ltc2627 are dual 16-, 14- and 12-bit, 2.7v to 5.5v rail-to-rail voltage output dacs in a 12-lead dfn package. they have built-in high performance output buffers and are guaranteed monotonic. these parts establish new board-density benchmarks for 16- and 14-bit dacs and advance performance standards for output drive and load regulation in single-supply, voltage-output dacs. the parts use a 2-wire, i 2 c compatible serial interface. the ltc2607/ltc2617/ltc2627 operate in both the standard mode (clock rate of 100khz) and the fast mode (clock rate of 400khz). an asynchronous dac update pin ( ldac ) is also included. the ltc2607/ltc2617/ltc2627 incorporate a power-on reset circuit. during power-up, the voltage outputs rise less than 10mv above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. the power-on reset circuit resets the ltc2607-1/ltc2617-1/ ltc2627-1 to mid-scale. the voltage outputs stay at mid- scale until a valid write and update takes place. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245 and 6891433. patent pending. a pplications n smallest pin-compatible dual dacs: ltc2607: 16 bits ltc2617: 14 bits ltc2627: 12 bits n guaranteed monotonic over temperature n 27 selectable addresses n 400khz i 2 c interface n wide 2.7v to 5.5v supply range n low power operation: 260a per dac at 3v n power down to 1a, max n high rail-to-rail output drive (15ma, min) n ultralow crosstalk (30v) n double-buffered data latches n asynchronous dac update pin n ltc2607/ltc2617/ltc2627: power-on reset to zero scale n ltc2607-1/ltc2617-1/ltc2627-1: power-on reset to mid-scale n tiny (3mm 4mm) 12-lead dfn package n mobile communications n process control and industrial automation n instrumentation n automatic test equipment differential nonlinearity (ltc2607) 9 8 11 10 5 6 2 1 4 3 2-wire interface ca0 ca1 ldac scl sda reflo gnd ref v cc ca2 32-bit shift register input register input register dac register dac register 7 12-/14-/16-bit dac v outb 12 12-/14-/16-bit dac v outa 2607 bd01a code 0 16384 32768 49152 65535 dnl (lsb) 2607 bd01b 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v cc = 5v v ref = 4.096v
ltc2607/ltc2617/ltc2627 26071727fa p in c on f iguration ab solute m aximum r atings any pin to gnd ............................................ C0.3v to 6v any pin to v cc ............................................. C6v to 0.3v maximum junction temperature .......................... 125c storage temperature range .................. C65c to 125c lead temperature (soldering, 10 sec)................... 300c operating temperature range: ltc2607c/ltc2617c/ltc2627c ltc2607c-1/ltc2617c-1/ltc2627c-1 .... 0c to 70c ltc2607i/ltc2617i/ltc2627i ltc2607i-1/ltc2617i-1/ltc2627i-1 ....C40c to 85c (note 1) top view 13 de12 package 12-lead (4mm s 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 v outa reflo gnd ref v cc v outb ca0 ca1 ldac scl sda ca2 7 6 t jmax = 125c, q ja = 43c/w exposed pad (pin 13) is gnd, must be soldered to pcb o r d er i n f ormation lead free finish tape and reel part marking* package description temperature range ltc2607cde#pbf ltc2607cde#trpbf 2607 12-lead (4mm s 3mm) plastic dfn 0c to 70c ltc2607ide#pbf ltc2607ide#trpbf 2607 12-lead (4mm s 3mm) plastic dfn C40c to 85c ltc2607cde-1#pbf ltc2607cde-1#trpbf 26071 12-lead (4mm s 3mm) plastic dfn 0c to 70c ltc2607ide-1#pbf ltc2607ide-1#trpbf 26071 12-lead (4mm s 3mm) plastic dfn C40c to 85c ltc2617cde#pbf ltc2617cde#trpbf 2617 12-lead (4mm s 3mm) plastic dfn 0c to 70c ltc2617ide#pbf ltc2617ide#trpbf 2617 12-lead (4mm s 3mm) plastic dfn C40c to 85c ltc2617cde-1#pbf ltc2617cde-1#trpbf 26171 12-lead (4mm s 3mm) plastic dfn 0c to 70c ltc2617ide-1#pbf ltc2617ide-1#trpbf 26171 12-lead (4mm s 3mm) plastic dfn C40c to 85c ltc2627cde#pbf ltc2627cde#trpbf 2627 12-lead (4mm s 3mm) plastic dfn 0c to 70c ltc2627ide#pbf ltc2627ide#trpbf 2627 12-lead (4mm s 3mm) plastic dfn C40c to 85c ltc2627cde-1#pbf ltc2627cde-1#trpbf 26271 12-lead (4mm s 3mm) plastic dfn 0c to 70c ltc2627ide-1#pbf ltc2627ide-1#trpbf 26271 12-lead (4mm s 3mm) plastic dfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc2607/ltc2617/ltc2627 26071727fa e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), reflo = 0v, v out unloaded, unless otherwise noted. symbol parameter conditions ltc2627/ltc2627-1 ltc2617/ltc2617-1 ltc2607/ltc2607-1 units min typ max min typ max min typ max dc performance resolution l 12 14 16 bits monotonicity (note 2) l 12 14 16 bits dnl differential nonlinearity (note 2) l 0.5 1 1 lsb inl integral nonlinearity (note 2) l 1.5 4 5 16 19 64 lsb load regulation v ref = v cc = 5v, mid-scale i out = 0ma to 15ma sourcing i out = 0ma to 15ma sinking l l 0.02 0.03 0.125 0.125 0.1 0.1 0.5 0.5 0.35 0.42 2 2 lsb/ma lsb/ma v ref = v cc = 2.7v, mid-scale i out = 0ma to 7.5ma sourcing i out = 0ma to 7.5ma sinking l l 0.04 0.05 0.25 0.25 0.2 0.2 1 1 0.7 0.8 4 4 lsb/ma lsb/ma zse zero-scale error code = 0 l 1 9 1 9 1 9 mv v os offset error (note 6) l 1 9 1 9 1 9 mv v os temperature coeffcient 7 7 7 v/c ge gain error l 0.15 0.7 0.15 0.7 0.15 0.7 %fsr gain temperature coeffcient 4 4 4 ppm/c the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), reflo = 0v, v out unloaded, unless otherwise noted. symbol parameter conditions min typ max units psr power supply rejection v cc 10% C80 db r out dc output impedance v ref = v cc = 5v, mid-scale; C15ma i out 15ma v ref = v cc = 2.7v, mid-scale; C7.5ma i out 7.5ma l l 0.032 0.035 0.15 0.15 dc crosstalk (note 4) due to full scale output change (note 5) due to load current change due to powering down (per channel) 4 3 30 v v/ma v i sc short-circuit output current v cc = 5.5v, v ref = 5.5v code: zero scale; forcing output to v cc code: full scale; forcing output to gnd l l 15 15 36 37 60 60 ma ma v cc = 2.7v, v ref = 2.7v code: zero scale; forcing output to v cc code: full scale; forcing output to gnd l l 7.5 7.5 22 30 50 50 ma ma reference input input voltage range l 0 v cc v resistance normal mode l 44 64 80 k capacitance 30 pf i ref reference current, power down mode dac powered down l 0.001 1 a
ltc2607/ltc2617/ltc2627 26071727fa e lectrical c haracteristics symbol parameter conditions min typ max units power supply v cc positive supply voltage for specifed performance l 2.7 5.5 v i cc supply current v cc = 5v (note 3) v cc = 3v (note 3) dac powered down (note 3) v cc = 5v dac powered down (note 3) v cc = 3v l l l l 0.66 0.52 0.4 0.10 1.3 1 1 1 ma ma a a digital i/o (note 11) v il low level input voltage (sda and scl) l 0.3v cc v v ih high level input voltage (sda and scl) l 0.7v cc v v il(ldac) low level input voltage ( ldac) v cc = 4.5v to 5.5v v cc = 2.7v to 5.5v l l 0.8 0.6 v v v ih(ldac) high level input voltage ( ldac) v cc = 2.7v to 5.5v v cc = 2.7v to 3.6v l l 2.4 2.0 v v v il(can) low level input voltage on ca n (n = 0, 1, 2) see test circuit 1 l 0.15v cc v v ih(can) high level input voltage on can ( n = 0, 1, 2) see test circuit 1 l 0.85v cc v r inh resistance from can (n = 0, 1, 2) to v cc to set can = v cc see test circuit 2 l 10 k r inl resistance from can (n = 0, 1, 2) to gnd to set can = gnd see test circuit 2 l 10 k r inf resistance from can (n = 0, 1, 2) to v cc or gnd to set can = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 9) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance note 12 l 10 pf c b capacitive load for each bus line l 400 pf c cax external capacitive load on address pins can (n = 0, 1, 2) l 10 pf the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), reflo = 0v, v out unloaded, unless otherwise noted.
ltc2607/ltc2617/ltc2627 26071727fa e lectrical c haracteristics t iming c haracteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: linearity and monotonicity are defned from code k l to code 2n C 1, where n is the resolution and k l is given by k l = 0.016(2 n /v ref ), rounded to the nearest whole code. for v ref = 4.096v and n = 16, k l = 256 and linearity is defned from code 256 to code 65,535. note 3: sda, scl and ldac at 0v or v cc , ca0, ca1 and ca2 floating. note 4: dc crosstalk is measured with v cc = 5v and v ref = 4.096v, with the measured dac at mid-scale, unless otherwise noted. symbol parameter conditions min typ max units v cc = 2.7v to 5.5v f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 9) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 9) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s t 1 falling edge of 9th clock of the 3rd input byte to ldac high or low transition l 400 ns t 2 ldac low pulse width l 20 ns the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (see figure 1) (notes 10, 11) the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ref = 4.096v (v cc = 5v), ref = 2.048v (v cc = 2.7v), reflo = 0v, v out unloaded, unless otherwise noted. symbol parameter conditions ltc2627/ltc2627-1 ltc2617/ltc2617-1 ltc2607/ltc2607-1 units min typ max min typ max min typ max ac performance t s settling time (note 7) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 7 7 9 7 9 10 s s s settling time for 1lsb step (note 8) 0.024% (1lsb at 12 bits) 0.006% (1lsb at 14 bits) 0.0015% (1lsb at 16 bits) 2.7 2.7 4.8 2.7 4.8 5.2 s s s voltage output slew rate 0.8 0.8 0.8 v/s capacitive load driving 1000 1000 1000 pf glitch impulse at mid-scale transition 12 12 12 nv ? s multiplying bandwidth 180 180 180 khz e n output voltage noise density at f = 1khz at f = 10khz 120 100 120 100 120 100 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz 15 15 15 v p-p note 5: r l = 2k to gnd or v cc . note 6: inferred from measurement at code k l (note 2) and at full scale. note 7: v cc = 5v, v ref = 4.096v. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 200pf to gnd. note 8: v cc = 5v, v ref = 4.096v. dac is stepped 1lsb between half scale and half scale C 1. load is 2k in parallel with 200pf to gnd. note 9: c b = capacitance of one bus line in pf. note 10: all values refer to v ih(min) and v il(max) levels. note 11: these specifcations apply to ltc2607/ltc2607-1, ltc2617/ltc2617-1, ltc2627/ltc2627-1. note 12: guaranteed by design and not production tested.
ltc2607/ltc2617/ltc2627 26071727fa t ypical p er f ormance c haracteristics dnl vs temperature inl vs v ref dnl vs v ref settling to 1lsb settling of full-scale step integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature ltc2607 code 0 16384 32768 49152 65535 inl (lsb) 2607 g01 32 24 16 8 0 ?8 ?16 ?24 ?32 v cc = 5v v ref = 4.096v code 0 16384 32768 49152 65535 dnl (lsb) 2607 g02 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v cc = 5v v ref = 4.096v temperature (c) ?50 ?30 ?10 10 30 50 70 90 inl (lsb) 2607 g03 32 24 16 8 0 ?8 ?16 ?24 ?32 v cc = 5v v ref = 4.096v inl (pos) inl (neg) temperature (c) ?50 ?30 ?10 10 30 50 70 90 dnl (lsb) 2607 g04 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v cc = 5v v ref = 4.096v dnl (pos) dnl (neg) v ref (v) 0 1 2 3 4 5 inl (lsb) 2607 g05 32 24 16 8 0 ?8 ?16 ?24 ?32 v cc = 5.5v inl (pos) inl (neg) v ref (v) 0 1 2 3 4 5 dnl (lsb) 2607 g06 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 v cc = 5.5v dnl (pos) dnl (neg) 2s/div 2607 g07 v out 100v/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 9th clock of 3rd data byte 9.7s settling to 1lsb v cc = 5v, v ref = 4.096v code 512 to 65535 step average of 2048 events scl 2v/div v out 100v/div 9th clock of 3rd data byte 12.3s 5s/div 2607 g08
ltc2607/ltc2617/ltc2627 26071727fa t ypical p er f ormance c haracteristics integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb ltc2617 ltc2627 code 0 4096 8192 12288 16383 inl (lsb) 2607 g09 8 6 4 2 0 ?2 ?4 ?6 ?8 v cc = 5v v ref = 4.096v code 0 4096 8192 12288 16383 dnl (lsb) 2607 g10 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v cc = 5v v ref = 4.096v 2s/div 2607 g11 v out 100v/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 8.9s 9th clock of 3rd data byte code 0 1024 2048 3072 4095 inl (lsb) 2607 g12 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 v cc = 5v v ref = 4.096v code 0 1024 2048 3072 4095 dnl (lsb) 2607 g13 v cc = 5v v ref = 4.096v 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 2s/div 2607 g14 v out 1mv/div scl 2v/div v cc = 5v, v ref = 4.096v 1/4-scale to 3/4-scale step r l = 2k, c l = 200pf average of 2048 events 6.8s 9th clock of 3rd data byte
ltc2607/ltc2617/ltc2627 26071727fa zero-scale error vs temperature gain error vs temperature offset error vs v cc gain error vs v cc i cc shutdown vs v cc current limiting load regulation offset error vs temperature ltc2607/ltc2617/ltc2627 i out (ma) ?40 ?30 ?20 ?10 0 10 20 30 40 ?v out (v) 2607 g15 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 v ref = v cc = 5v v ref = v cc = 3v v ref = v cc = 5v v ref = v cc = 3v code = mid-scale i out (ma) ?35 ?25 ?15 ?5 5 15 25 35 ?v out (mv) 2607 g16 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v ref = v cc = 5v code = mid-scale v ref = v cc = 3v temperature (c) ?50 ?30 ?10 10 30 50 70 90 offset error (mv) 2607 g17 3 2 1 0 ?1 ?2 ?3 temperature (c) ?50 ?30 ?10 10 30 50 70 90 zero-scale error (mv) 2607 g18 3 2.5 2.0 1.5 1.0 0.5 0 temperature (c) ?50 ?30 ?10 10 30 50 70 90 gain error (%fsr) 2607 g19 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 offset error (mv) 2607 g20 3 2 1 0 ?1 ?2 ?3 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 2607 g21 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 v cc (v) 2.5 3 3.5 4 4.5 5 5.5 i cc (na) 2607 g22 450 400 350 300 250 200 150 100 50 0 t ypical p er f ormance c haracteristics
ltc2607/ltc2617/ltc2627 26071727fa t ypical p er f ormance c haracteristics headroom at rails vs output current power-on reset to midscale large-signal response mid-scale glitch impulse power-on reset to zeroscale ltc2607/ltc2617/ltc2627 supply current vs logic voltage supply current vs logic voltage logic voltage (v) 0 500 i cc (a) 550 650 700 750 3 3.5 4 4.5 950 2607 g28 600 0.5 1 1.5 2 2.5 5 800 850 900 v cc = 5v sweep ldac ov to v cc logic voltage (v) 0 i cc (a) 800 900 1000 3 5 2607 g029 700 600 500 1 2 4 1100 1200 1300 hystersis 370mv v cc = 5v sweep scl and sda ov to v cc and v cc to ov 2.5s/div v out 0.5v/div 2607 g23 v ref = v cc = 5v 1/4-scale to 3/4-scale i out (ma) 0 1 2 3 4 5 6 7 8 9 10 v out (v) 2607 g26 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5v sourcing 3v sourcing 3v sinking 5v sinking v out 10mv/div 250s/div 2607 g25 v cc 1v/div 4mv peak 1v/div 500s/div 2607 g27 v cc v out v ref = v cc v out 10mv/div scl 2v/div 2.5s/div 2607 g24 transition from ms-1 to ms transition from ms to ms-1 9th clock of 3rd data byte multiplying bandwidth output voltage noise, 0.1hz to 10hz frequency (hz) 1k db 0 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 1m 2607 g30 10k 100k v cc = 5v v ref (dc) = 2v v ref (ac) = 0.2v p-p code = full scale v out 10v/div seconds 0 1 2 3 4 5 6 7 8 9 10 2607 g31
ltc2607/ltc2617/ltc2627 0 26071727fa p in functions ca0 (pin 1): chip address bit 0. tie this pin to v cc , gnd or leave it foating to select an i 2 c slave address for the part (table 1). ca1 (pin 2): chip address bit 1. tie this pin to v cc , gnd or leave it foating to select an i 2 c slave address for the part (table 1). ldac (pin 3): asynchronous dac update. a falling edge of this input after four bytes have been written into the part immediately updates the dac register with the contents of the input register. a low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part wakes up sleeping dacs without up- dating the dac output. software power-down is disabled when ldac is low. ldac is disabled when tied high. scl (pin 4): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . sda (pin 5): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this pin is high impedance while data is shifted in and an open- drain n-channel output during acknowledgment. requires a pull-up resistor or current source to v cc. ca2 (pin 6): chip address bit 2. tie this pin to v cc , gnd or leave it foating to select an i 2 c slave address for the part (table 1). v outb (pin 7): dac analog voltage output. the output range is v reflo to v ref . v cc (pin 8): supply voltage input. 2.7v v cc 5.5v. ref (pin 9): reference voltage input. the input range is v reflo v ref v cc . gnd (pin 10): analog ground. reflo (pin 11): reference low. the voltage at this pin sets the zero scale (zs) voltage of all dacs. the v reflo pin can be used at voltages up to 1v for v cc = 5v, or 100mv for v cc = 3v. v outa (pin 12): dac analog voltage output. the output range is v reflo to v ref . exposed pad (pin 13): ground. must be soldered to pcb ground. short-circuit output current vs v out (sinking) short-circuit output current vs v out (sourcing) 1v/div 0 0 10ma/div 10 20 30 40 50 1 2 3 4 2607 g32 5 6 v cc = 5.5v v ref = 5.6v code = 0 v out swept 0v to v cc 1v/div 0 ?50 10ma/div ?40 ?30 ?20 ?10 0 1 2 3 4 2607 g33 5 6 v cc = 5.5v v ref = 5.6v code = full scale v out swept v cc to 0v ltc2607/ltc2617/ltc2627 t ypical p er f ormance c haracteristics
ltc2607/ltc2617/ltc2627 26071727fa block diagram t est c ircuits 9 8 11 10 5 6 2 1 4 3 2-wire interface ca0 ca1 ldac scl sda reflo gnd ref v cc ca2 32-bit shift register input register input register dac register dac register 7 12-/14-/16-bit dac v outb 12 12-/14-/16-bit dac v outa 2607 bd 100 r inh /r inl /r inf v ih(can) /v il(can) can gnd 2607 tc v dd test circuit 2 test circuit 1 can
ltc2607/ltc2617/ltc2627 26071727fa t iming diagrams figure 2a figure 2b figure 1 sda t f s t r t low t hd(sta) all voltage levels refer to v ih(min) and v il(max) levels t hd(dat) t su(dat) t su(sta) t hd(sta) t su(sto) t sp t buf t r t f t high scl s p s 2607 f01 ack ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 2607 f02a ack t 1 start sda sa6 sa5 sa4 sa3 slave address sa2 sa1 sa0 scl ldac c2c3 c1 c0 a3 a2 a1 a0 ack 1st data byte 2nd data byte 3rd data byte t 2 9th clock of 3rd data byte t 1 scl ldac 2607 f02b
ltc2607/ltc2617/ltc2627 26071727fa o peration specifcations. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the v cc power should not be removed from the ltc2607/ltc2617/ltc2627 when the i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. the ltc2607/ltc2617/ltc2627 are receive-only (slave) devices. the master can write to the ltc2607/ltc2617/ ltc2627. the ltc2607/ltc2617/ltc2627 do not respond to a read from the master. the start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has fnished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the lat- est byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the slave-receiver must pull down the sda bus line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2607/ltc2617/ltc2627 respond to a write by a master in this manner. the ltc2607/ltc2617/ltc2627 do not acknowledge a read (retains sda high during the period of the acknowledge clock pulse). chip address the state of ca0, ca1 and ca2 decides the slave address of the part. the pins ca0, ca1 and ca2 can be each set to any one of three states: v cc , gnd or foat. this results power-on reset the ltc2607/ltc2617/ltc2627 clear the outputs to zero scale when power is frst applied, making system initialization consistent and repeatable. the ltc2607-1/ l tc2617 - 1/ltc2627-1 set the voltage outputs to midscale when power is frst applied. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2607/ ltc2617/ltc2627 contain circuitry to reduce the power- on glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. for example, if the power supply is ramped to 5v in 1ms, the analog outputs rise less than 10mv above ground (typ) during power-on. see power-on reset glitch in the typical performance characteristics section. power supply sequencing the voltage at ref (pin 9) should be kept within the range C0.3v v ref v cc + 0.3v (see absolute maximum rat- ings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 8) is in transition. transfer function the digital-to-analog transfer function is: v k v v v out ideal n ref reflo reflo ( ) = ? ? ? ? ? ? ? ( ) + 2 where k is the decimal equivalent of the binary dac input code, n is the resolution and v ref is the voltage at ref (pin 6). serial digital interface the ltc2607/ltc2617/ltc2627 communicate with a host using the standard 2-wire i 2 c interface. the timing diagrams (figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c
ltc2607/ltc2617/ltc2627 26071727fa in 27 selectable addresses for the part. the slave address assignments are shown in table 1. table 1. slave address map ca2 ca1 ca0 sa6 sa5 sa4 sa3 sa2 sa1 sa0 gnd gnd gnd 0 0 1 0 0 0 0 gnd gnd float 0 0 1 0 0 0 1 gnd gnd v cc 0 0 1 0 0 1 0 gnd float gnd 0 0 1 0 0 1 1 gnd float float 0 1 0 0 0 0 0 gnd float v cc 0 1 0 0 0 0 1 gnd v cc gnd 0 1 0 0 0 1 0 gnd v cc float 0 1 0 0 0 1 1 gnd v cc v cc 0 1 1 0 0 0 0 float gnd gnd 0 1 1 0 0 0 1 float gnd float 0 1 1 0 0 1 0 float gnd v cc 0 1 1 0 0 1 1 float float gnd 1 0 0 0 0 0 0 float float float 1 0 0 0 0 0 1 float float v cc 1 0 0 0 0 1 0 float v cc gnd 1 0 0 0 0 1 1 float v cc float 1 0 1 0 0 0 0 float v cc v cc 1 0 1 0 0 0 1 v cc gnd gnd 1 0 1 0 0 1 0 v cc gnd float 1 0 1 0 0 1 1 v cc gnd v cc 1 1 0 0 0 0 0 v cc float gnd 1 1 0 0 0 0 1 v cc float float 1 1 0 0 0 1 0 v cc float v cc 1 1 0 0 0 1 1 v cc v cc gnd 1 1 1 0 0 0 0 v cc v cc float 1 1 1 0 0 0 1 v cc v cc v cc 1 1 1 0 0 1 0 global address 1 1 1 0 0 1 1 in addition to the address selected by the address pins, the parts also respond to a global address. this address allows a common write to all ltc2607, ltc2617 and ltc2627 parts to be accomplished with one 3-byte write transaction on the i 2 c bus. the global address is a 7-bit on-chip hardwired address and is not selectable by ca0, ca1 and ca2. o peration the addresses corresponding to the states of ca0, ca1 and ca2 and the global address are shown in table 1. the maximum capacitive load allowed on the address pins (ca0, ca1 and ca2) is 10pf, as these pins are driven during address detection to determine if they are foating. write word protocol the master initiates communication with the ltc2607/ ltc2617/ltc2627 with a start condition and a 7-bit slave address followed by the write bit (w) = 0. the ltc2607/ ltc2617/ltc2627 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by ca0, ca1 and ca2) or the global address. the master then transmits three bytes of data. the ltc2607/ltc2617/ltc2627 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2607/ltc2617/ltc2627 executes the command specifed in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2607/ltc2617/ltc2627 do not acknowledge the extra bytes of data (sda is high during the 9th clock). the format of the three data bytes is shown in figure 3. the frst byte of the input word consists of the 4-bit com- mand word c3-c0, and 4-bit dac address a3-a0. the next two bytes consist of the 16-bit data word. the 16-bit data word consists of the 16-, 14- or 12-bit input code, msb to lsb, followed by 0, 2 or 4 dont care bits (ltc2607, ltc2617 and ltc2627 respectively). a typical ltc2607 write transaction is shown in figure 4. the command (c3-c0) and address (a3-a0) assignments are shown in table 2. the frst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected dac, n. an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram.
ltc2607/ltc2617/ltc2627 26071727fa o peration table 2 command* c3 c2 c1 c0 0 0 0 0 write to input register 0 0 0 1 update (power up) dac register 0 0 1 1 write to and update (power up) 0 1 0 0 power down 1 1 1 1 no operation address* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 1 1 1 1 all dacs *command and address codes not shown are reserved and should not be used. power-down mode for power-constrained applications, the power-down mode can be used to reduce the supply current whenever one or both of the dac outputs are not needed. when in power- down, the buffer amplifers, bias circuits and reference input are disabled and draw essentially zero current. the dac outputs are put into a high impedance state, and the output pins are passively pulled to v reflo through 90k resistors. input-register and dac-register contents are not disturbed during power-down. either or both dac channels can be put into power-down mode by using command 0100b in combination with the figure 3 c3 1st data byte input word (ltc2607) write word protocol for ltc2607/ltc2617/ltc1627 c2 c1 c0 a3 a2 a1 a0 d13d14d15 s w a slave address 1st data byte d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a 2nd data byte a 3rd data byte a p 2607 f03 2nd data byte input word 3rd data byte c3 1st data byte input word (ltc2617) c2 c1 c0 a3 a2 a1 a0 d11d12d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 2nd data byte 3rd data byte c3 1st data byte input word (ltc2627) c2 c1 c0 a3 a2 a1 a0 d9d10d11 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x 2nd data byte 3rd data byte appropriate dac address. the 16-bit data word is ignored. the supply and reference currents are reduced by approxi- mately 50% for each dac powered down; the effective resistance at ref (pin 9) rises accordingly, becoming a high-impedance input (typically > 1g) when both dacs are powered down. normal operation can be resumed by executing any command which includes a dac update, as shown in table 2 or performing an asychronous update ( ldac ) as described in the next section. the selected dac is powered up as its voltage output is updated. when a dac in powered- down state is powered up and updated, normal settling is delayed. if one of the two dacs is in a powered- down state prior to the update command, the power up delay is 5s. if on the other hand, both dacs are powered down, the main bias generation circuit has been automatically shut down in addition to the dac amplifers and reference input and so the power up delay time is 12s (for v cc = 5v) or 30s (for v cc = 3v) asynchronous dac update using ldac in addition to the update commands shown in table 2, the ldac pin asynchronously updates the dac registers with the contents of the input registers. asynchronous update is disabled when the input word is being clocked into the part.
ltc2607/ltc2617/ltc2627 26071727fa o peration if a complete input word has been written to the part, a low on the ldac pin causes the dac registers to be updated with the contents of the input registers. if the input word is being written to the part, a low going pulse on the ldac pin before the completion of three bytes of data powers up the dacs but does not cause the outputs to be updated. if ldac remains low after a complete input word has been written to the part, then ldac is recognized, the command specifed in the 24-bit word just transferred is executed and the dac outputs updated. the dacs are powered up when ldac is taken low, inde- pendent of any activity on the i 2 c bus. if ldac is low at the falling edge of the 9th clock of the 3rd byte of data, it inhibits any software power-down command that was specifed in the input word. ldac is disabled when tied high. voltage output both of the two rail-to-rail amplifers have guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the amplifers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output volt- age per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the amplifers dc output impedance is 0.035 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the amplifers are stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation performance is achieved in part by separating the signal and power grounds as reflo and gnd pins, respectively. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps the digital signals away from the sensitive analog signals and facili- tates the use of separate digital and analog ground planes that have minimal interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin functions as a return path for power supply currents in the device and should be connected to analog ground. resistance from the gnd pin to the analog power supply return should be as low as possible. resistance here will add directly to the channel resistance of the output device when sinking load current. when a zero scale dac output voltage of zero is required, the reflo pin should be connected to system star ground. any shared trace resistance between reflo and gnd pins is undesirable since it adds to the effective dc output impedance (typi- cally 0.035 ) of the part. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in figure 5b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 5c. no full-scale limiting will occur if v ref is less than v cc C fse. offset and linearity are defned and tested over the region of the dac transfer function where no output limiting can occur.
ltc2607/ltc2617/ltc2627 26071727fa o peration figure 4. typical ltc2607 input waveformprogramming dac output for full scale figure 5. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for codes near full scale ack ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 2607 f04 ack start x = don?t care stop full-scale voltage zero-scale voltage sda sa6 sa5 sa4 sa3 sa2 sa1 sa0 scl v out c2c3 c3 c2 c1 c0 a3 a2 a1 a0 c1 c0 a3 a2 a1 a0 ack command d15 d14 d13 d12 d11 d10 d9 d8 ms data d7 d6 d5 d4 d3 d2 d1 d0 ls data sa6 sa5 sa4 sa3 sa2 sa1 sa0 wr slave address 2607 f05 input code (b) output voltage negative offset 0v 32, 768 0 65, 535 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse
ltc2607/ltc2617/ltc2627 26071727fa p ackage description de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d) 4.00 p0.10 (2 sides) 3.00 p0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom view?exposed pad 1.70 p 0.10 0.75 p0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 s 45o chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 p0.05 0.70 p0.05 3.60 p0.05 package outline 3.30 p0.10 0.25 p 0.05 0.50 bsc 1.70 p 0.05 3.30 p0.05 0.50 bsc 0.25 p 0.05
ltc2607/ltc2617/ltc2627 26071727fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number a 1/10 revised features added pin confguration and updated order information added text to serial digital interface section 1 2 13
ltc2607/ltc2617/ltc2627 0 26071727fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0110 rev a ? printed in usa r elate d p arts t ypical a pplication part number description comments ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.096v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1654 dual 14-bit rail-to-rail v out dac programmable speed/power, 3.5s/750a, 8s/450a ltc1655/ltc1655l single 16-bit v out dacs with serial interface in so-8 v cc = 5v(3v), low power, deglitched ltc1657/ltc1657l parallel 5v/3v 16-bit v out dacs low power, deglitched, rail-to-rail v out ltc1660/ltc1665 octal 10/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1664 quad 10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 parallel 16-bit voltage output dac precision 16-bit settling in 2s for 10v step ltc2600/ltc2610/ ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2601/ltc2611/ ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614/ ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2605/ltc2615/ ltc2625 octal 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2606/ltc2616/ ltc2626 16-/14-/12-bit v out dacs with i 2 c interface 270a per dac, 2.7v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a range per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac demo circuit schematic. onboard 20-bit adc measures key performance parameters 9 8 7 10 3 1 2 6 4 5 5 6 2 8 6 1 2607 ta01 10, 13 i 2 c bus v ref 1v to 5v 0.1f spi bus 5v 5v 7 3 100 7.5k dac output b 12 4 100 7.5k dac output a f o sck sdo cs v cc fs set gnd zs set ltc2422 v cc ref gnd reflo ltc2607 ldac ca0 ca1 ca2 scl sda v outb v outa ch 1 ch 0

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